#ifndef _TABLES_PIXEL_CLK_SET_H
#define _TABLES_PIXEL_CLK_SET_H
/*
 * Copyright 2011 Sylvain Bertrand (digital.ragnarok@gmail.com)
 * This fork is protected by the GNU affero GPLv3 with additionnal rights
 * Original code from Advanced Micro Devices, Inc.
 */

#define CRTC0		0
#define CRTC1		1
#define CRTC2		2
#define CRTC3		3
#define CRTC4		4
#define CRTC5		5
#define CRTC_INVALID	0xff

#define PPLL1		0
#define PPLL2		1
#define DCPLL		2
#define PPLL0		2
#define EXT_PLL1	8
#define EXT_PLL2	9
#define EXT_CLK		10
#define PPLL_INVALID	0xff

struct pixel_clk_set_params_v1_5 {
	u8 crtc;		/* CRTC0~5, indicate the CRTC controller to
				   drive the pixel clock. Not used for DCPLL
				   case. */
	union {
		u8 rsvd0;
		u8 frac_fb_div;	/* not supposed to be around */
	};
	__le16 pixel_clk;	/* Target the pixel clock to drive the CRTC
				   timing. 0 means disable PPLL/DCPLL. 10kHz unit. */
	__le16 fb_div;		/* feedback divider integer part */
	u8 post_div;		/* post divider */
	u8 ref_div;		/* Reference divider */
	u8 ppll;		/* PPLL1/PPLL2/DCPLL */
	u8 trans_id;		/* transmitter object id */
	u8 enc_mode;		/* encoder mode */
	u8 misc_info;		/* [0]   Force program PPLL 
				   [1]   when VGA timing is used
				   [3:2] HDMI panel bit depth
				         0: 24bpp 
				         1: 30bpp 
				         2: 32bpp
				   [4]   RefClock source for PPLL
				         0: XTLAIN (default mode)
				         1: other external clock source, which
				            is pre-defined by VBIOS depend on
				            the feature required.
				   [7:5] reserved */
	__le32 fb_div_dec_frac;	/* 20bits feedback divider decimal fraction
				   part, range from 1~999999 (0.000001 to
				   0.999999) */

} __packed;
#endif
